Multitech MT5600SMI Specifiche Pagina 70
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Chapter 3 – SocketModem (MT5634SMI-34 & MT5634SMI-92)
Multi-Tech Systems, Inc. Universal Socket Hardware Guide for Developers (S000342C) 70
SocketModem Parallel Interface Internal
Registers
The SocketModem parallel interface is a mimic of a 16C550A UART. It is similar to the MIMIC interface used in the
Zilog Z80189. The SocketModem mimic (MMM) takes advantage of this standard interface while replacing the serial
to parallel data transfer with a less complicated parallel to parallel data transfer.
The MMM interface controls an 8-bit parallel data transfer which is typically interrupt driven. Interrupts usually indicate
one or both of two conditions: (1) the receive (RX) FIFO has either reached a trigger level or time-out condition and
needs to be emptied and/or (2) the transmit (TX) FIFO is empty and waiting for more data from the Host. An interrupt
can also be triggered by a change in the modem status register (i.e., loss of carrier) or by the occurrence of errors in
the line status register (overrun, parity, framing, break detect).
In addition to the receive and transmit FIFOs, there are twelve other control/status registers called the MMM register
set which can be accessed through this interface.
Overview
SocketModem MIMIC (MMM) Operation
Data flow through MMM is bi-directional. Simultaneously, data can flow from the host through the transmit FIFO to the
SocketModem controller, and data can flow from SocketModem controller through the receive FIFO to the Host. In
the receive path, 8-bit data is asynchronously received (from the SocketModem controller) by the receive FIFO where
it is stored along with associated three error bits. The error bits must arrive (via a SocketModem controller I/O write to
MMM shadow line status register) prior to receiving the actual data bits. The error bits are then temporarily stored so
they may be written, with associated data bits, to the 11-bit wide RX FIFO.
After every data write, the RX FIFO write pointer is incremented. RX FIFO trigger levels, data ready signal, and time-
out counter are checked to see if a Host interrupt needs to be sent. The data ready signal will be activated and MMM
sits poised to accept another data word.
We highly recommend the host should read the MMM IIR register to determine the type of interrupt. Then it might
check bit 7 of the LSR to see if there are any errors in the data currently residing in the receive FIFO. Finally, it will
(1) alternately read a data word through the RX FIFO read pointer and the error bits via the MMM LSR until the FIFO
is empty, or (2) read successive data words (knowing there were no errors in the FIFO) until the trigger count is met.
A similar sequence occurs when data flows in the other direction (from host through transmit FIFO), except there is
no error bit manipulation/checking involved.
FIFO Operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit-0. You can set
the receive trigger level via FCR bits 6/7. The receiver FIFO section includes a time-out function to ensure data is
delivered to the external host. An interrupt is generated whenever the Receive Holding Register (RHR) has not
been read following the loading of a character or the receive trigger level has been reached.
Receive (RX) FIFO
The RX FIFO can be configured to be 16 words deep and 11 bits wide. Each word in the RX FIFO consists of 8
data bits and 3 error bits. The RX block of the MMM contains read and write pointers and status flag circuitry
that need only to be presented with data (for input), reset, read/write control signals, and read/write clock signals.
The RX block of the MMM internally manages the FIFO register file and pointers, and it provides simultaneous
read/write capability (no contention problems).
The RX block of the MMM provides data (for output), FIFO full flag, FIFO empty flag, and an almost full flag
which uses an associated predefined trigger level (obtained from the MMM FCR control register) to signal when
the trigger level has been met. Four possible trigger levels may be selected by programming bits 6-7 of the FCR
control register.
- Universal Socket 1
- Connectivity 1
- Table of Contents 3
- Chapter 1 7
- Chapter 1 - Universal Socket 8
- Commands 9
- Universal Pin Descriptions 10
- Design Considerations 13
- Maximum Component Height 16
- SocketModem Developer Board 17
- Telecom Approvals 24
- Label Examples 27
- Industry Canada 28
- South African Statement 29
- Flash Upgrade 30
- Serial Port Upgrade 31
- Ethernet Port Upgrade 32
- Programming the Modem 33
- Other Programming Concerns 34
- Wireless Account Activation 36
- Replacement Parts 39
- Chapter 2 40
- Chapter 2 – SocketModem 41
- (MT5600SMI & MT5656SMI) 41
- Developer Kit 42
- Parallel Configuration 45
- Current Modems 46
- Overview 49
- FCR – FIFO Control Register 52
- LCR – Line Control Register 54
- LSR – Line Status Register 56
- MSR – Modem Status Register 57
- SCR – Scratch Register 58
- Divisor Registers 58
- Microphone and Speaker 60
- Recommended Parts 61
- Chapter 3 62
- Chapter 3 – SocketModem 63
- Timing Requirements 69
- Registers 70
- Time Out Interrupts 72
- FCR – FIFO Control 74
- LCR – Line Control 74
- MCR – Modem Control 74
- LSR – Line Status 75
- MSR – Modem Status 75
- SCR – Scratch 76
- DLL – Divisor Latch (LSByte) 76
- DLM – Divisor Latch (MSByte) 76
- Chapter 4 79
- Chapter 4 – SocketModem 80
- (MT2456SMI-22) 80
- Applications Notes 85
- Chapter 5 87
- Chapter 5 – SocketModem IP 88
- (MT2456SMI-IP) 88
- Chapter 6 95
- (MTXCSEM) 96
- Application Notes 100
- Chapter 7 101
- Chapter 7 – SocketModem ISDN 102
- (MT128SMI) 102
- Technical Specifications 103
- Serial Configuration 104
- Electrical Characteristics 105
- MT128SMI Developer Board 106
- MT128SMI Schematics 107
- Chapter 8 111
- Chapter 8 – SocketModem GPRS 112
- (MTSMC-G) 112
- Mechanical Dimensions 114
- SocketModem Configuration 115
- MMCX Plug 120
- MMCX / SMA Adapter 120
- Antenna Cable 120
- Chapter 9 121
- Chapter 9 – SocketModem CDMA 122
- (MTSMC-C) 122
- CDMA Antenna 127
- Radio Characteristics 127
- Chapter 10 128
- Chapter 10 – SocketWireless 129
- Bluetooth (MTS2BTSMI) 129
- Category Description 131
- Changing Configuration 135
- Antenna Requirements 136
- Antenna 136
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